1. Field of the Invention
The present invention generally relates to testing of printed circuit boards, or substrates, on which are mounted integrated circuits (ICs), and, more specifically, to a method and circuit for determining the location of an unintended break in a printed wire connecting two IC pins to simplify repair of the circuit board or substrate.
2. Description of Related Art
As printed circuit boards populated with ICs get smaller and more dense, it becomes more difficult to quickly diagnose and repair the boards, especially if the IC package is a ball grid array (BGA). On their underside, BGAs have an array of solder pads that are completely hidden from view when the pads are soldered to a board, as shown in FIG. 1 and in profile in FIG. 2, and therefore it is difficult to visually verify the soldered connections. As a result, digital boundary scan is becoming a popular design for test (DFT) technique to permit quick verification of board-level connections between ICs.
A digital boundary scan test comprises enabling a serial shift register that accesses the pins of an IC, shifting in logic values to each output pin, updating the logic value at each output pin with the value shifted in, parallel capturing the logic values received at each input pin, and serially shifting out the captured values for examination by a tester.
When a short circuit is detected between two signals, it is usually easy to predict the physical location of the defect because there is typically only one location where a pair of signals is close to one another and near a soldered connection. However, when an open is detected in a wire connecting an output pin and an intended input pin, it can be difficult to locate the position of the defect because no other signals are involved. For a board that was inspected before it was populated with components, the most likely location for an open in a connection between two IC pins is the solder connection to one of the two pins involved.
Diagnosing the location of opens and shorts in populated circuit boards is important for allowing quick repair of the boards, specifically for facilitating the re-soldering of only the defective pin or array of pins. There are several prior art techniques for determining the location of these defects.
Crook et al. U.S. Pat. No. 5,254,953 granted on Oct. 19, 1993 for xe2x80x9cIdentification of Pin-Open Faults by Capacitive Coupling Through the Integrated Circuit Packagexe2x80x9d, applies a 10 kHz signal via a metal plate that has the same area as an IC whose pins are to be tested for open circuit faults. The metal plate is physically placed a short distance (within a few millimeters) above the IC and hence capacitively couples to the pins (leadframe legs) of the IC package. The signal is received via a mechanical probe that probes the printed wire that is supposed to be connected to a pin of the IC. The signal amplitude detected by the sensor is larger if the pin is connected to the probed wire than if there is an open solder joint. This approach is not suitable for BGAs because the IC pins are underneath the IC die and hence have much less capacitance to the metal plate, there is no leadframe, the pins have much less area than non-BGA ICs, and many wires are not accessible to be probed.
Hamblin U.S. Pat. No. 5,736,862 granted on Apr. 7, 1998 for xe2x80x9cSystem for Detecting Faults in Connections Between Integrated Circuit Board Tracesxe2x80x9d, applies a stimulus signal to another pin of one of the ICs whose pin is to be tested for an open circuit, and the signal is detected via a mechanical probe that is placed on a mid-point of the wire under test. The stimulus signal is capacitively coupled between the pin to which it is applied and the pin that is supposed to be connected to the wire under test, through inherent capacitance that typically exists between any two pins of any IC. This approach does not require access to the pins under test, but does require precision in the placement of the mechanical probes and probe access to every wire to be diagnosed.
Brooks U.S. Pat. No. 6,104,198 granted on Aug. 15, 2000 for xe2x80x9cTesting the Integrity of An Electrical Connection to a Device Using an Onboard Controllable Signal Sourcexe2x80x9d, generates a stimulus signal within a first IC and the stimulus signal is detected via a capacitively-coupled sensor plate placed above a second IC whose pin is supposed to be connected to a pin of the first IC. This approach addresses the problem of inaccessibility of IC pins, but still requires a sensor plate that must be precisely placed physically close to the circuit board. For many populated circuit boards, it is not practical to place a sensor plate close enough to the component side of the circuit board, and often ground plane layers within the circuit board, such as shown in FIG. 2, prevent meaningful measurements when the sensor plate is on the other side of the circuit board.
A paper entitled xe2x80x9cOpens Board Test Coverage: When is 99% Really 40%?xe2x80x9d, by M. Tegethoff et al, published in the Proceedings of the 1996 International Test Conference (ITC), describes detecting open circuits in printed circuit boards containing ICs by using X-ray laminography. This equipment uses X-rays to identify open circuits between BGA pins and printed wires underneath. The equipment is quite expensive (more than $100K), large, and relatively slow.
A booklet entitled xe2x80x9cIEEE Standard for a Mixed Signal Test Busxe2x80x9d, published in 1999 by the Institute for Electrical and Electronic Engineers (IEEE), which is also known as IEEE STD. 1149.4-1999, or simply 1149.4, describes the general architecture of a mixed signal test bus. The architecture is shown in FIG. 4. The capabilities of this test bus have been described in several published papers, including, xe2x80x9cDesign, Fabrication, and Use of Mixed-Signal IC Testability Structuresxe2x80x9d by K. Parker et al, published in the Proceedings of the 1997 ITC. This test bus was primarily designed to permit the measurement of discrete passive components, including capacitors and resistors, that are connected to the pins of ICs which might otherwise be inaccessible due to the density of the circuit boards containing these ICs and components. It is possible to apply a stimulus to a pin, via one of these test buses, and to simultaneously monitor the pin""s response voltage via another of these test buses, and to thus determine the capacitance of a discrete capacitor that has been connected to the pin, such as that shown in FIG. 3. The published papers regarding 1149.4 anticipate that if the value of a capacitor is measured to be approximately zero, it can be deduced that the capacitor is missing or some other open circuit defect exists, but it is not taught by the prior art how to deduce where the open defect in the circuit physically exists.
Thus, there is a need for a method which determines the physical location of open circuit defects in wires connected to IC pins using only wire access to a circuit board and to do so using only low cost, commonly available electronic test equipment, without requiring mechanical probes, plates, or other such precision electro-mechanical equipment, so that the diagnosis can be performed at a field repair office as well as at an initial manufacturing site.
The present invention provides a method and a circuit for determining the location of an open defect in a wire connected to an IC pin by providing digitally controlled electrical access to the IC pin via a function or test bus connected to the IC, a stimulus signal within or external to the IC, signal detection circuitry within or external to the IC, and means for comparing a measured capacitance of the pin to the value expected for the pin without a connection. The method includes the steps of applying a stimulus signal to the pin connected to the wire via the digitally controlled electrical access, detecting the resultant signal at the pin via the digitally controlled electrical access, comparing the detected value to an expected value that is based on the capacitance of the pin and the expected capacitance per unit length of the wire.
When a wire connects two IC pins, the inventive method further includes simply determining which pin the open defect is closer to, based on which pin has less wire capacitance.